    IF :LNOT::DEF:INCLUDED_CYFITTERRV_INC
INCLUDED_CYFITTERRV_INC EQU 1
    GET cydevicerv.inc
    GET cydevicerv_trm.inc

; Rx_1
Rx_1__0__MASK EQU 0x01
Rx_1__0__PC EQU CYREG_PRT4_PC0
Rx_1__0__PORT EQU 4
Rx_1__0__SHIFT EQU 0
Rx_1__AG EQU CYREG_PRT4_AG
Rx_1__AMUX EQU CYREG_PRT4_AMUX
Rx_1__BIE EQU CYREG_PRT4_BIE
Rx_1__BIT_MASK EQU CYREG_PRT4_BIT_MASK
Rx_1__BYP EQU CYREG_PRT4_BYP
Rx_1__CTL EQU CYREG_PRT4_CTL
Rx_1__DM0 EQU CYREG_PRT4_DM0
Rx_1__DM1 EQU CYREG_PRT4_DM1
Rx_1__DM2 EQU CYREG_PRT4_DM2
Rx_1__DR EQU CYREG_PRT4_DR
Rx_1__INP_DIS EQU CYREG_PRT4_INP_DIS
Rx_1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
Rx_1__LCD_EN EQU CYREG_PRT4_LCD_EN
Rx_1__MASK EQU 0x01
Rx_1__PORT EQU 4
Rx_1__PRT EQU CYREG_PRT4_PRT
Rx_1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
Rx_1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
Rx_1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
Rx_1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
Rx_1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
Rx_1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
Rx_1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
Rx_1__PS EQU CYREG_PRT4_PS
Rx_1__SHIFT EQU 0
Rx_1__SLW EQU CYREG_PRT4_SLW

; Tx_1
Tx_1__0__MASK EQU 0x02
Tx_1__0__PC EQU CYREG_PRT4_PC1
Tx_1__0__PORT EQU 4
Tx_1__0__SHIFT EQU 1
Tx_1__AG EQU CYREG_PRT4_AG
Tx_1__AMUX EQU CYREG_PRT4_AMUX
Tx_1__BIE EQU CYREG_PRT4_BIE
Tx_1__BIT_MASK EQU CYREG_PRT4_BIT_MASK
Tx_1__BYP EQU CYREG_PRT4_BYP
Tx_1__CTL EQU CYREG_PRT4_CTL
Tx_1__DM0 EQU CYREG_PRT4_DM0
Tx_1__DM1 EQU CYREG_PRT4_DM1
Tx_1__DM2 EQU CYREG_PRT4_DM2
Tx_1__DR EQU CYREG_PRT4_DR
Tx_1__INP_DIS EQU CYREG_PRT4_INP_DIS
Tx_1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
Tx_1__LCD_EN EQU CYREG_PRT4_LCD_EN
Tx_1__MASK EQU 0x02
Tx_1__PORT EQU 4
Tx_1__PRT EQU CYREG_PRT4_PRT
Tx_1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
Tx_1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
Tx_1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
Tx_1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
Tx_1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
Tx_1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
Tx_1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
Tx_1__PS EQU CYREG_PRT4_PS
Tx_1__SHIFT EQU 1
Tx_1__SLW EQU CYREG_PRT4_SLW

; UART_BUART
UART_BUART_sRX_RxBitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
UART_BUART_sRX_RxBitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
UART_BUART_sRX_RxBitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
UART_BUART_sRX_RxBitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
UART_BUART_sRX_RxBitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
UART_BUART_sRX_RxBitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK
UART_BUART_sRX_RxBitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
UART_BUART_sRX_RxBitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK
UART_BUART_sRX_RxBitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
UART_BUART_sRX_RxBitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
UART_BUART_sRX_RxBitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL
UART_BUART_sRX_RxBitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL
UART_BUART_sRX_RxBitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL
UART_BUART_sRX_RxBitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
UART_BUART_sRX_RxBitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
UART_BUART_sRX_RxBitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
UART_BUART_sRX_RxBitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK
UART_BUART_sRX_RxBitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
UART_BUART_sRX_RxBitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
UART_BUART_sRX_RxBitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK
UART_BUART_sRX_RxBitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
UART_BUART_sRX_RxBitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
UART_BUART_sRX_RxBitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
UART_BUART_sRX_RxBitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL
UART_BUART_sRX_RxBitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL
UART_BUART_sRX_RxBitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST
UART_BUART_sRX_RxShifter_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0
UART_BUART_sRX_RxShifter_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1
UART_BUART_sRX_RxShifter_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0
UART_BUART_sRX_RxShifter_u0__16BIT_D1_REG EQU CYREG_B0_UDB06_07_D1
UART_BUART_sRX_RxShifter_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
UART_BUART_sRX_RxShifter_u0__16BIT_F0_REG EQU CYREG_B0_UDB06_07_F0
UART_BUART_sRX_RxShifter_u0__16BIT_F1_REG EQU CYREG_B0_UDB06_07_F1
UART_BUART_sRX_RxShifter_u0__A0_A1_REG EQU CYREG_B0_UDB06_A0_A1
UART_BUART_sRX_RxShifter_u0__A0_REG EQU CYREG_B0_UDB06_A0
UART_BUART_sRX_RxShifter_u0__A1_REG EQU CYREG_B0_UDB06_A1
UART_BUART_sRX_RxShifter_u0__D0_D1_REG EQU CYREG_B0_UDB06_D0_D1
UART_BUART_sRX_RxShifter_u0__D0_REG EQU CYREG_B0_UDB06_D0
UART_BUART_sRX_RxShifter_u0__D1_REG EQU CYREG_B0_UDB06_D1
UART_BUART_sRX_RxShifter_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
UART_BUART_sRX_RxShifter_u0__F0_F1_REG EQU CYREG_B0_UDB06_F0_F1
UART_BUART_sRX_RxShifter_u0__F0_REG EQU CYREG_B0_UDB06_F0
UART_BUART_sRX_RxShifter_u0__F1_REG EQU CYREG_B0_UDB06_F1
UART_BUART_sRX_RxShifter_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
UART_BUART_sRX_RxShifter_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
UART_BUART_sRX_RxSts__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
UART_BUART_sRX_RxSts__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
UART_BUART_sRX_RxSts__3__MASK EQU 0x08
UART_BUART_sRX_RxSts__3__POS EQU 3
UART_BUART_sRX_RxSts__4__MASK EQU 0x10
UART_BUART_sRX_RxSts__4__POS EQU 4
UART_BUART_sRX_RxSts__5__MASK EQU 0x20
UART_BUART_sRX_RxSts__5__POS EQU 5
UART_BUART_sRX_RxSts__MASK EQU 0x38
UART_BUART_sRX_RxSts__MASK_REG EQU CYREG_B0_UDB05_MSK
UART_BUART_sRX_RxSts__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
UART_BUART_sRX_RxSts__STATUS_REG EQU CYREG_B0_UDB05_ST
UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A0_REG EQU CYREG_B0_UDB03_04_A0
UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A1_REG EQU CYREG_B0_UDB03_04_A1
UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D0_REG EQU CYREG_B0_UDB03_04_D0
UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D1_REG EQU CYREG_B0_UDB03_04_D1
UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F0_REG EQU CYREG_B0_UDB03_04_F0
UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F1_REG EQU CYREG_B0_UDB03_04_F1
UART_BUART_sTX_sCLOCK_TxBitClkGen__A0_A1_REG EQU CYREG_B0_UDB03_A0_A1
UART_BUART_sTX_sCLOCK_TxBitClkGen__A0_REG EQU CYREG_B0_UDB03_A0
UART_BUART_sTX_sCLOCK_TxBitClkGen__A1_REG EQU CYREG_B0_UDB03_A1
UART_BUART_sTX_sCLOCK_TxBitClkGen__D0_D1_REG EQU CYREG_B0_UDB03_D0_D1
UART_BUART_sTX_sCLOCK_TxBitClkGen__D0_REG EQU CYREG_B0_UDB03_D0
UART_BUART_sTX_sCLOCK_TxBitClkGen__D1_REG EQU CYREG_B0_UDB03_D1
UART_BUART_sTX_sCLOCK_TxBitClkGen__DP_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
UART_BUART_sTX_sCLOCK_TxBitClkGen__F0_F1_REG EQU CYREG_B0_UDB03_F0_F1
UART_BUART_sTX_sCLOCK_TxBitClkGen__F0_REG EQU CYREG_B0_UDB03_F0
UART_BUART_sTX_sCLOCK_TxBitClkGen__F1_REG EQU CYREG_B0_UDB03_F1
UART_BUART_sTX_TxShifter_u0__16BIT_A0_REG EQU CYREG_B0_UDB02_03_A0
UART_BUART_sTX_TxShifter_u0__16BIT_A1_REG EQU CYREG_B0_UDB02_03_A1
UART_BUART_sTX_TxShifter_u0__16BIT_D0_REG EQU CYREG_B0_UDB02_03_D0
UART_BUART_sTX_TxShifter_u0__16BIT_D1_REG EQU CYREG_B0_UDB02_03_D1
UART_BUART_sTX_TxShifter_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
UART_BUART_sTX_TxShifter_u0__16BIT_F0_REG EQU CYREG_B0_UDB02_03_F0
UART_BUART_sTX_TxShifter_u0__16BIT_F1_REG EQU CYREG_B0_UDB02_03_F1
UART_BUART_sTX_TxShifter_u0__A0_A1_REG EQU CYREG_B0_UDB02_A0_A1
UART_BUART_sTX_TxShifter_u0__A0_REG EQU CYREG_B0_UDB02_A0
UART_BUART_sTX_TxShifter_u0__A1_REG EQU CYREG_B0_UDB02_A1
UART_BUART_sTX_TxShifter_u0__D0_D1_REG EQU CYREG_B0_UDB02_D0_D1
UART_BUART_sTX_TxShifter_u0__D0_REG EQU CYREG_B0_UDB02_D0
UART_BUART_sTX_TxShifter_u0__D1_REG EQU CYREG_B0_UDB02_D1
UART_BUART_sTX_TxShifter_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
UART_BUART_sTX_TxShifter_u0__F0_F1_REG EQU CYREG_B0_UDB02_F0_F1
UART_BUART_sTX_TxShifter_u0__F0_REG EQU CYREG_B0_UDB02_F0
UART_BUART_sTX_TxShifter_u0__F1_REG EQU CYREG_B0_UDB02_F1
UART_BUART_sTX_TxSts__0__MASK EQU 0x01
UART_BUART_sTX_TxSts__0__POS EQU 0
UART_BUART_sTX_TxSts__1__MASK EQU 0x02
UART_BUART_sTX_TxSts__1__POS EQU 1
UART_BUART_sTX_TxSts__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
UART_BUART_sTX_TxSts__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST
UART_BUART_sTX_TxSts__2__MASK EQU 0x04
UART_BUART_sTX_TxSts__2__POS EQU 2
UART_BUART_sTX_TxSts__3__MASK EQU 0x08
UART_BUART_sTX_TxSts__3__POS EQU 3
UART_BUART_sTX_TxSts__MASK EQU 0x0F
UART_BUART_sTX_TxSts__MASK_REG EQU CYREG_B1_UDB05_MSK
UART_BUART_sTX_TxSts__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
UART_BUART_sTX_TxSts__STATUS_REG EQU CYREG_B1_UDB05_ST

; UART_IntClock
UART_IntClock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0
UART_IntClock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1
UART_IntClock__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2
UART_IntClock__CFG2_SRC_SEL_MASK EQU 0x07
UART_IntClock__INDEX EQU 0x02
UART_IntClock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
UART_IntClock__PM_ACT_MSK EQU 0x04
UART_IntClock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
UART_IntClock__PM_STBY_MSK EQU 0x04

; UART_RXInternalInterrupt
UART_RXInternalInterrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
UART_RXInternalInterrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
UART_RXInternalInterrupt__INTC_MASK EQU 0x08
UART_RXInternalInterrupt__INTC_NUMBER EQU 3
UART_RXInternalInterrupt__INTC_PRIOR_NUM EQU 7
UART_RXInternalInterrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3
UART_RXInternalInterrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
UART_RXInternalInterrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0

; UART_TEST_BUART
UART_TEST_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A0_REG EQU CYREG_B0_UDB07_08_A0
UART_TEST_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A1_REG EQU CYREG_B0_UDB07_08_A1
UART_TEST_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D0_REG EQU CYREG_B0_UDB07_08_D0
UART_TEST_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D1_REG EQU CYREG_B0_UDB07_08_D1
UART_TEST_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
UART_TEST_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F0_REG EQU CYREG_B0_UDB07_08_F0
UART_TEST_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F1_REG EQU CYREG_B0_UDB07_08_F1
UART_TEST_BUART_sTX_sCLOCK_TxBitClkGen__A0_A1_REG EQU CYREG_B0_UDB07_A0_A1
UART_TEST_BUART_sTX_sCLOCK_TxBitClkGen__A0_REG EQU CYREG_B0_UDB07_A0
UART_TEST_BUART_sTX_sCLOCK_TxBitClkGen__A1_REG EQU CYREG_B0_UDB07_A1
UART_TEST_BUART_sTX_sCLOCK_TxBitClkGen__D0_D1_REG EQU CYREG_B0_UDB07_D0_D1
UART_TEST_BUART_sTX_sCLOCK_TxBitClkGen__D0_REG EQU CYREG_B0_UDB07_D0
UART_TEST_BUART_sTX_sCLOCK_TxBitClkGen__D1_REG EQU CYREG_B0_UDB07_D1
UART_TEST_BUART_sTX_sCLOCK_TxBitClkGen__DP_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
UART_TEST_BUART_sTX_sCLOCK_TxBitClkGen__F0_F1_REG EQU CYREG_B0_UDB07_F0_F1
UART_TEST_BUART_sTX_sCLOCK_TxBitClkGen__F0_REG EQU CYREG_B0_UDB07_F0
UART_TEST_BUART_sTX_sCLOCK_TxBitClkGen__F1_REG EQU CYREG_B0_UDB07_F1
UART_TEST_BUART_sTX_TxShifter_u0__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0
UART_TEST_BUART_sTX_TxShifter_u0__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1
UART_TEST_BUART_sTX_TxShifter_u0__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0
UART_TEST_BUART_sTX_TxShifter_u0__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1
UART_TEST_BUART_sTX_TxShifter_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
UART_TEST_BUART_sTX_TxShifter_u0__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0
UART_TEST_BUART_sTX_TxShifter_u0__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1
UART_TEST_BUART_sTX_TxShifter_u0__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1
UART_TEST_BUART_sTX_TxShifter_u0__A0_REG EQU CYREG_B0_UDB04_A0
UART_TEST_BUART_sTX_TxShifter_u0__A1_REG EQU CYREG_B0_UDB04_A1
UART_TEST_BUART_sTX_TxShifter_u0__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1
UART_TEST_BUART_sTX_TxShifter_u0__D0_REG EQU CYREG_B0_UDB04_D0
UART_TEST_BUART_sTX_TxShifter_u0__D1_REG EQU CYREG_B0_UDB04_D1
UART_TEST_BUART_sTX_TxShifter_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
UART_TEST_BUART_sTX_TxShifter_u0__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1
UART_TEST_BUART_sTX_TxShifter_u0__F0_REG EQU CYREG_B0_UDB04_F0
UART_TEST_BUART_sTX_TxShifter_u0__F1_REG EQU CYREG_B0_UDB04_F1
UART_TEST_BUART_sTX_TxSts__0__MASK EQU 0x01
UART_TEST_BUART_sTX_TxSts__0__POS EQU 0
UART_TEST_BUART_sTX_TxSts__1__MASK EQU 0x02
UART_TEST_BUART_sTX_TxSts__1__POS EQU 1
UART_TEST_BUART_sTX_TxSts__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
UART_TEST_BUART_sTX_TxSts__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
UART_TEST_BUART_sTX_TxSts__2__MASK EQU 0x04
UART_TEST_BUART_sTX_TxSts__2__POS EQU 2
UART_TEST_BUART_sTX_TxSts__3__MASK EQU 0x08
UART_TEST_BUART_sTX_TxSts__3__POS EQU 3
UART_TEST_BUART_sTX_TxSts__MASK EQU 0x0F
UART_TEST_BUART_sTX_TxSts__MASK_REG EQU CYREG_B0_UDB03_MSK
UART_TEST_BUART_sTX_TxSts__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
UART_TEST_BUART_sTX_TxSts__STATUS_REG EQU CYREG_B0_UDB03_ST

; UART_TEST_IntClock
UART_TEST_IntClock__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
UART_TEST_IntClock__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
UART_TEST_IntClock__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
UART_TEST_IntClock__CFG2_SRC_SEL_MASK EQU 0x07
UART_TEST_IntClock__INDEX EQU 0x01
UART_TEST_IntClock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
UART_TEST_IntClock__PM_ACT_MSK EQU 0x02
UART_TEST_IntClock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
UART_TEST_IntClock__PM_STBY_MSK EQU 0x02

; UART_TEST_TXInternalInterrupt
UART_TEST_TXInternalInterrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
UART_TEST_TXInternalInterrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
UART_TEST_TXInternalInterrupt__INTC_MASK EQU 0x20
UART_TEST_TXInternalInterrupt__INTC_NUMBER EQU 5
UART_TEST_TXInternalInterrupt__INTC_PRIOR_NUM EQU 7
UART_TEST_TXInternalInterrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5
UART_TEST_TXInternalInterrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
UART_TEST_TXInternalInterrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0

; UART_TXInternalInterrupt
UART_TXInternalInterrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
UART_TXInternalInterrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
UART_TXInternalInterrupt__INTC_MASK EQU 0x10
UART_TXInternalInterrupt__INTC_NUMBER EQU 4
UART_TXInternalInterrupt__INTC_PRIOR_NUM EQU 7
UART_TXInternalInterrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
UART_TXInternalInterrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
UART_TXInternalInterrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0

; TIMER_CLOCK
TIMER_CLOCK__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0
TIMER_CLOCK__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1
TIMER_CLOCK__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2
TIMER_CLOCK__CFG2_SRC_SEL_MASK EQU 0x07
TIMER_CLOCK__INDEX EQU 0x00
TIMER_CLOCK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
TIMER_CLOCK__PM_ACT_MSK EQU 0x01
TIMER_CLOCK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
TIMER_CLOCK__PM_STBY_MSK EQU 0x01

; TIMER_TimerUDB
TIMER_TimerUDB_rstSts_stsreg__0__MASK EQU 0x01
TIMER_TimerUDB_rstSts_stsreg__0__POS EQU 0
TIMER_TimerUDB_rstSts_stsreg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
TIMER_TimerUDB_rstSts_stsreg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
TIMER_TimerUDB_rstSts_stsreg__2__MASK EQU 0x04
TIMER_TimerUDB_rstSts_stsreg__2__POS EQU 2
TIMER_TimerUDB_rstSts_stsreg__3__MASK EQU 0x08
TIMER_TimerUDB_rstSts_stsreg__3__POS EQU 3
TIMER_TimerUDB_rstSts_stsreg__MASK EQU 0x0D
TIMER_TimerUDB_rstSts_stsreg__MASK_REG EQU CYREG_B1_UDB07_MSK
TIMER_TimerUDB_rstSts_stsreg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
TIMER_TimerUDB_rstSts_stsreg__STATUS_REG EQU CYREG_B1_UDB07_ST
TIMER_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
TIMER_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
TIMER_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
TIMER_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
TIMER_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
TIMER_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK
TIMER_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
TIMER_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK
TIMER_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
TIMER_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__7__MASK EQU 0x80
TIMER_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__7__POS EQU 7
TIMER_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
TIMER_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG EQU CYREG_B1_UDB04_CTL
TIMER_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL
TIMER_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__COUNT_REG EQU CYREG_B1_UDB04_CTL
TIMER_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL
TIMER_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__MASK EQU 0x80
TIMER_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
TIMER_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
TIMER_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__PERIOD_REG EQU CYREG_B1_UDB04_MSK
TIMER_TimerUDB_sT32_timerdp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
TIMER_TimerUDB_sT32_timerdp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
TIMER_TimerUDB_sT32_timerdp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
TIMER_TimerUDB_sT32_timerdp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1
TIMER_TimerUDB_sT32_timerdp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
TIMER_TimerUDB_sT32_timerdp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0
TIMER_TimerUDB_sT32_timerdp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1
TIMER_TimerUDB_sT32_timerdp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1
TIMER_TimerUDB_sT32_timerdp_u0__A0_REG EQU CYREG_B1_UDB04_A0
TIMER_TimerUDB_sT32_timerdp_u0__A1_REG EQU CYREG_B1_UDB04_A1
TIMER_TimerUDB_sT32_timerdp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1
TIMER_TimerUDB_sT32_timerdp_u0__D0_REG EQU CYREG_B1_UDB04_D0
TIMER_TimerUDB_sT32_timerdp_u0__D1_REG EQU CYREG_B1_UDB04_D1
TIMER_TimerUDB_sT32_timerdp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
TIMER_TimerUDB_sT32_timerdp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1
TIMER_TimerUDB_sT32_timerdp_u0__F0_REG EQU CYREG_B1_UDB04_F0
TIMER_TimerUDB_sT32_timerdp_u0__F1_REG EQU CYREG_B1_UDB04_F1
TIMER_TimerUDB_sT32_timerdp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
TIMER_TimerUDB_sT32_timerdp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
TIMER_TimerUDB_sT32_timerdp_u1__16BIT_A0_REG EQU CYREG_B1_UDB05_06_A0
TIMER_TimerUDB_sT32_timerdp_u1__16BIT_A1_REG EQU CYREG_B1_UDB05_06_A1
TIMER_TimerUDB_sT32_timerdp_u1__16BIT_D0_REG EQU CYREG_B1_UDB05_06_D0
TIMER_TimerUDB_sT32_timerdp_u1__16BIT_D1_REG EQU CYREG_B1_UDB05_06_D1
TIMER_TimerUDB_sT32_timerdp_u1__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
TIMER_TimerUDB_sT32_timerdp_u1__16BIT_F0_REG EQU CYREG_B1_UDB05_06_F0
TIMER_TimerUDB_sT32_timerdp_u1__16BIT_F1_REG EQU CYREG_B1_UDB05_06_F1
TIMER_TimerUDB_sT32_timerdp_u1__A0_A1_REG EQU CYREG_B1_UDB05_A0_A1
TIMER_TimerUDB_sT32_timerdp_u1__A0_REG EQU CYREG_B1_UDB05_A0
TIMER_TimerUDB_sT32_timerdp_u1__A1_REG EQU CYREG_B1_UDB05_A1
TIMER_TimerUDB_sT32_timerdp_u1__D0_D1_REG EQU CYREG_B1_UDB05_D0_D1
TIMER_TimerUDB_sT32_timerdp_u1__D0_REG EQU CYREG_B1_UDB05_D0
TIMER_TimerUDB_sT32_timerdp_u1__D1_REG EQU CYREG_B1_UDB05_D1
TIMER_TimerUDB_sT32_timerdp_u1__DP_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
TIMER_TimerUDB_sT32_timerdp_u1__F0_F1_REG EQU CYREG_B1_UDB05_F0_F1
TIMER_TimerUDB_sT32_timerdp_u1__F0_REG EQU CYREG_B1_UDB05_F0
TIMER_TimerUDB_sT32_timerdp_u1__F1_REG EQU CYREG_B1_UDB05_F1
TIMER_TimerUDB_sT32_timerdp_u2__16BIT_A0_REG EQU CYREG_B1_UDB06_07_A0
TIMER_TimerUDB_sT32_timerdp_u2__16BIT_A1_REG EQU CYREG_B1_UDB06_07_A1
TIMER_TimerUDB_sT32_timerdp_u2__16BIT_D0_REG EQU CYREG_B1_UDB06_07_D0
TIMER_TimerUDB_sT32_timerdp_u2__16BIT_D1_REG EQU CYREG_B1_UDB06_07_D1
TIMER_TimerUDB_sT32_timerdp_u2__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
TIMER_TimerUDB_sT32_timerdp_u2__16BIT_F0_REG EQU CYREG_B1_UDB06_07_F0
TIMER_TimerUDB_sT32_timerdp_u2__16BIT_F1_REG EQU CYREG_B1_UDB06_07_F1
TIMER_TimerUDB_sT32_timerdp_u2__A0_A1_REG EQU CYREG_B1_UDB06_A0_A1
TIMER_TimerUDB_sT32_timerdp_u2__A0_REG EQU CYREG_B1_UDB06_A0
TIMER_TimerUDB_sT32_timerdp_u2__A1_REG EQU CYREG_B1_UDB06_A1
TIMER_TimerUDB_sT32_timerdp_u2__D0_D1_REG EQU CYREG_B1_UDB06_D0_D1
TIMER_TimerUDB_sT32_timerdp_u2__D0_REG EQU CYREG_B1_UDB06_D0
TIMER_TimerUDB_sT32_timerdp_u2__D1_REG EQU CYREG_B1_UDB06_D1
TIMER_TimerUDB_sT32_timerdp_u2__DP_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
TIMER_TimerUDB_sT32_timerdp_u2__F0_F1_REG EQU CYREG_B1_UDB06_F0_F1
TIMER_TimerUDB_sT32_timerdp_u2__F0_REG EQU CYREG_B1_UDB06_F0
TIMER_TimerUDB_sT32_timerdp_u2__F1_REG EQU CYREG_B1_UDB06_F1
TIMER_TimerUDB_sT32_timerdp_u3__16BIT_A0_REG EQU CYREG_B1_UDB07_08_A0
TIMER_TimerUDB_sT32_timerdp_u3__16BIT_A1_REG EQU CYREG_B1_UDB07_08_A1
TIMER_TimerUDB_sT32_timerdp_u3__16BIT_D0_REG EQU CYREG_B1_UDB07_08_D0
TIMER_TimerUDB_sT32_timerdp_u3__16BIT_D1_REG EQU CYREG_B1_UDB07_08_D1
TIMER_TimerUDB_sT32_timerdp_u3__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
TIMER_TimerUDB_sT32_timerdp_u3__16BIT_F0_REG EQU CYREG_B1_UDB07_08_F0
TIMER_TimerUDB_sT32_timerdp_u3__16BIT_F1_REG EQU CYREG_B1_UDB07_08_F1
TIMER_TimerUDB_sT32_timerdp_u3__A0_A1_REG EQU CYREG_B1_UDB07_A0_A1
TIMER_TimerUDB_sT32_timerdp_u3__A0_REG EQU CYREG_B1_UDB07_A0
TIMER_TimerUDB_sT32_timerdp_u3__A1_REG EQU CYREG_B1_UDB07_A1
TIMER_TimerUDB_sT32_timerdp_u3__D0_D1_REG EQU CYREG_B1_UDB07_D0_D1
TIMER_TimerUDB_sT32_timerdp_u3__D0_REG EQU CYREG_B1_UDB07_D0
TIMER_TimerUDB_sT32_timerdp_u3__D1_REG EQU CYREG_B1_UDB07_D1
TIMER_TimerUDB_sT32_timerdp_u3__DP_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
TIMER_TimerUDB_sT32_timerdp_u3__F0_F1_REG EQU CYREG_B1_UDB07_F0_F1
TIMER_TimerUDB_sT32_timerdp_u3__F0_REG EQU CYREG_B1_UDB07_F0
TIMER_TimerUDB_sT32_timerdp_u3__F1_REG EQU CYREG_B1_UDB07_F1

; Isr_rx
Isr_rx__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
Isr_rx__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
Isr_rx__INTC_MASK EQU 0x01
Isr_rx__INTC_NUMBER EQU 0
Isr_rx__INTC_PRIOR_NUM EQU 7
Isr_rx__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
Isr_rx__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
Isr_rx__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0

; Isr_tx
Isr_tx__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
Isr_tx__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
Isr_tx__INTC_MASK EQU 0x04
Isr_tx__INTC_NUMBER EQU 2
Isr_tx__INTC_PRIOR_NUM EQU 7
Isr_tx__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2
Isr_tx__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
Isr_tx__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0

; Isr_timer
Isr_timer__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
Isr_timer__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
Isr_timer__INTC_MASK EQU 0x02
Isr_timer__INTC_NUMBER EQU 1
Isr_timer__INTC_PRIOR_NUM EQU 7
Isr_timer__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
Isr_timer__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
Isr_timer__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0

; DEBUG_LED_1
DEBUG_LED_1__0__MASK EQU 0x01
DEBUG_LED_1__0__PC EQU CYREG_PRT2_PC0
DEBUG_LED_1__0__PORT EQU 2
DEBUG_LED_1__0__SHIFT EQU 0
DEBUG_LED_1__AG EQU CYREG_PRT2_AG
DEBUG_LED_1__AMUX EQU CYREG_PRT2_AMUX
DEBUG_LED_1__BIE EQU CYREG_PRT2_BIE
DEBUG_LED_1__BIT_MASK EQU CYREG_PRT2_BIT_MASK
DEBUG_LED_1__BYP EQU CYREG_PRT2_BYP
DEBUG_LED_1__CTL EQU CYREG_PRT2_CTL
DEBUG_LED_1__DM0 EQU CYREG_PRT2_DM0
DEBUG_LED_1__DM1 EQU CYREG_PRT2_DM1
DEBUG_LED_1__DM2 EQU CYREG_PRT2_DM2
DEBUG_LED_1__DR EQU CYREG_PRT2_DR
DEBUG_LED_1__INP_DIS EQU CYREG_PRT2_INP_DIS
DEBUG_LED_1__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
DEBUG_LED_1__LCD_EN EQU CYREG_PRT2_LCD_EN
DEBUG_LED_1__MASK EQU 0x01
DEBUG_LED_1__PORT EQU 2
DEBUG_LED_1__PRT EQU CYREG_PRT2_PRT
DEBUG_LED_1__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
DEBUG_LED_1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
DEBUG_LED_1__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
DEBUG_LED_1__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
DEBUG_LED_1__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
DEBUG_LED_1__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
DEBUG_LED_1__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
DEBUG_LED_1__PS EQU CYREG_PRT2_PS
DEBUG_LED_1__SHIFT EQU 0
DEBUG_LED_1__SLW EQU CYREG_PRT2_SLW

; Miscellaneous
BCLK__BUS_CLK__HZ EQU 24000000
BCLK__BUS_CLK__KHZ EQU 24000
BCLK__BUS_CLK__MHZ EQU 24
CYDEV_CHIP_DIE_LEOPARD EQU 1
CYDEV_CHIP_DIE_PANTHER EQU 4
CYDEV_CHIP_DIE_PSOC4A EQU 2
CYDEV_CHIP_DIE_PSOC5LP EQU 5
CYDEV_CHIP_DIE_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_PSOC3 EQU 1
CYDEV_CHIP_FAMILY_PSOC4 EQU 2
CYDEV_CHIP_FAMILY_PSOC5 EQU 3
CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5
CYDEV_CHIP_JTAG_ID EQU 0x2E123069
CYDEV_CHIP_MEMBER_3A EQU 1
CYDEV_CHIP_MEMBER_4A EQU 2
CYDEV_CHIP_MEMBER_4D EQU 3
CYDEV_CHIP_MEMBER_5A EQU 4
CYDEV_CHIP_MEMBER_5B EQU 5
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B
CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED
CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
CYDEV_CHIP_REV_PANTHER_ES0 EQU 0
CYDEV_CHIP_REV_PANTHER_ES1 EQU 1
CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1
CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_3A_ES1 EQU 0
CYDEV_CHIP_REVISION_3A_ES2 EQU 1
CYDEV_CHIP_REVISION_3A_ES3 EQU 3
CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
CYDEV_CHIP_REVISION_4A_ES0 EQU 17
CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_4D_ES0 EQU 0
CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_5A_ES0 EQU 0
CYDEV_CHIP_REVISION_5A_ES1 EQU 1
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
CYDEV_CHIP_REVISION_5B_ES0 EQU 0
CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION
CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED
CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1
CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn
CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
CYDEV_CONFIGURATION_COMPRESSED EQU 1
CYDEV_CONFIGURATION_DMA EQU 0
CYDEV_CONFIGURATION_ECC EQU 1
CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED
CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED
CYDEV_CONFIGURATION_MODE_DMA EQU 2
CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1
CYDEV_DEBUG_ENABLE_MASK EQU 0x20
CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
CYDEV_DEBUGGING_DPS_Disable EQU 3
CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1
CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0
CYDEV_DEBUGGING_DPS_SWD EQU 2
CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6
CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV
CYDEV_DEBUGGING_ENABLE EQU 1
CYDEV_DEBUGGING_XRES EQU 0
CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
CYDEV_ECC_ENABLE EQU 0
CYDEV_HEAP_SIZE EQU 0x1000
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
CYDEV_INTR_RISING EQU 0x0000003F
CYDEV_PROJ_TYPE EQU 0
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
CYDEV_PROJ_TYPE_LOADABLE EQU 2
CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3
CYDEV_PROJ_TYPE_STANDARD EQU 0
CYDEV_PROTECTION_ENABLE EQU 0
CYDEV_STACK_SIZE EQU 0x4000
CYDEV_USE_BUNDLED_CMSIS EQU 1
CYDEV_VARIABLE_VDDA EQU 0
CYDEV_VDDA_MV EQU 5000
CYDEV_VDDD_MV EQU 5000
CYDEV_VDDIO0_MV EQU 5000
CYDEV_VDDIO1_MV EQU 5000
CYDEV_VDDIO2_MV EQU 5000
CYDEV_VDDIO3_MV EQU 5000
CYDEV_VIO0 EQU 5
CYDEV_VIO0_MV EQU 5000
CYDEV_VIO1 EQU 5
CYDEV_VIO1_MV EQU 5000
CYDEV_VIO2 EQU 5
CYDEV_VIO2_MV EQU 5000
CYDEV_VIO3 EQU 5
CYDEV_VIO3_MV EQU 5000
CYIPBLOCK_ARM_CM3_VERSION EQU 0
CYIPBLOCK_P3_ANAIF_VERSION EQU 0
CYIPBLOCK_P3_CAN_VERSION EQU 0
CYIPBLOCK_P3_CAPSENSE_VERSION EQU 0
CYIPBLOCK_P3_COMP_VERSION EQU 0
CYIPBLOCK_P3_DECIMATOR_VERSION EQU 0
CYIPBLOCK_P3_DFB_VERSION EQU 0
CYIPBLOCK_P3_DMA_VERSION EQU 0
CYIPBLOCK_P3_DRQ_VERSION EQU 0
CYIPBLOCK_P3_DSM_VERSION EQU 0
CYIPBLOCK_P3_EMIF_VERSION EQU 0
CYIPBLOCK_P3_I2C_VERSION EQU 0
CYIPBLOCK_P3_LCD_VERSION EQU 0
CYIPBLOCK_P3_LPF_VERSION EQU 0
CYIPBLOCK_P3_OPAMP_VERSION EQU 0
CYIPBLOCK_P3_PM_VERSION EQU 0
CYIPBLOCK_P3_SCCT_VERSION EQU 0
CYIPBLOCK_P3_TIMER_VERSION EQU 0
CYIPBLOCK_P3_USB_VERSION EQU 0
CYIPBLOCK_P3_VIDAC_VERSION EQU 0
CYIPBLOCK_P3_VREF_VERSION EQU 0
CYIPBLOCK_S8_GPIO_VERSION EQU 0
CYIPBLOCK_S8_IRQ_VERSION EQU 0
CYIPBLOCK_S8_SAR_VERSION EQU 0
CYIPBLOCK_S8_SIO_VERSION EQU 0
CYIPBLOCK_S8_UDB_VERSION EQU 0
DMA_CHANNELS_USED__MASK0 EQU 0x00000000
CYDEV_BOOTLOADER_ENABLE EQU 0
    ENDIF
    END
